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class="post-meta-separator">|</span><i class="fas fa-history fa-fw post-meta-icon"></i><span class="post-meta-label">更新于</span><time class="post-meta-date-updated" datetime="2021-08-31T09:07:33.699Z" title="更新于 2021-08-31 17:07:33">2021-08-31</time></span><span class="post-meta-categories"><span class="post-meta-separator">|</span><i class="fas fa-inbox fa-fw post-meta-icon"></i><a class="post-meta-categories" href="/categories/%E5%AD%A6%E4%B9%A0%E6%89%8B%E8%AE%B0/">学习手记</a><i class="fas fa-angle-right post-meta-separator"></i><i class="fas fa-inbox fa-fw post-meta-icon"></i><a class="post-meta-categories" href="/categories/%E5%AD%A6%E4%B9%A0%E6%89%8B%E8%AE%B0/%E7%A1%AC%E4%BB%B6%E8%AE%BE%E8%AE%A1/">硬件设计</a></span></div><div class="meta-secondline"><span class="post-meta-separator">|</span><span class="post-meta-pv-cv" id="" data-flag-title="【学习手记】堆栈电路的EDA设计"><i class="far fa-eye fa-fw post-meta-icon"></i><span class="post-meta-label">阅读量:</span><span id="busuanzi_value_page_pv"></span></span></div></div></div></header><main class="layout" id="content-inner"><div id="post"><article class="post-content" id="article-container"><h2 id="1-设计要求"><a href="#1-设计要求" class="headerlink" title="1. 设计要求"></a>1. 设计要求</h2><p>设计5字节的堆栈电路并进行仿真，电路使用8位并行接口，端口包括8位数据端口D、读写信号RD与WR、片选端口CS。当CS、WR产生下降沿时，电路通过8位并行接口将数据写入堆栈；当CS、RD产生下降沿时，电路通过8位并行接口按照“先入后出”的顺序，将堆栈数据依次送至数据总线D。</p>
<!-- hexo-inject:begin --><!-- hexo-inject:end --><h2 id="2-功能与电路逻辑分析"><a href="#2-功能与电路逻辑分析" class="headerlink" title="2. 功能与电路逻辑分析"></a>2. 功能与电路逻辑分析</h2><h3 id="2-1-功能分析"><a href="#2-1-功能分析" class="headerlink" title="2.1 功能分析"></a>2.1 功能分析</h3><p>堆栈是计算机系统中应用非常广泛的一种储存电路，它遵循先入后出的储存原则，常用于计算机控制过程中的一些重要的运行参数与数据的存储恢复。基本堆栈存储区STACK、堆栈指针SP，如图2.1所示。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/2.1.jpg" alt="图2.1 堆栈电路简化模型图"></p>
<p>当存入数据时，堆栈电路获取堆栈指针SP，计算对应的存储地址。然后将指定数据传送至相应的存储单元，则堆栈指针加1运算，即称之为“压栈”或“入栈”；读数据操作时，堆栈电路首先获取堆栈指针SP，堆栈指针则进行减1运算，随后计算地址信息，将对应存储单元的数据传送至数据总线，完成栈内数据的“出栈”操作。<br>在堆栈初始化状态时，堆栈指针SP指向图中的栈底。随堆栈操作的进行，根据栈操作的指令，堆栈指针依次加1（上移）或减1（下移），直至到达栈底或栈顶。</p>
<h3 id="2-2-实现原理"><a href="#2-2-实现原理" class="headerlink" title="2.2 实现原理"></a>2.2 实现原理</h3><p>堆栈电路设计通过写进程WrProc（压栈）、读进程RdProc（出栈）、指针控制进程PntCon与堆栈储存区DSeg共同实现。为便于电路描述，堆栈设计中特别设置堆栈的读指针pRd与写指针pWr，其中的写指针pWr与堆栈SP取值相同，读指针pRd的取值为pWr减1，与堆栈定义及操作完全一致。<br><br>写进程WrProc实现数据的压栈操作，进程响应器件并行接口的写操作，将写入的数据送入堆栈DSeg，完成压栈。同时，WrProc结合电路的读写状况调整写指针pWr；读进程RdProc实现数据的出栈操作，进程响应器件并行接口的读操作，将堆栈内数据送至器件的数据端口D，完成出栈；进程PntCon专门用于读指针的动态调整，进程根据器件读写状况计算堆栈的读指针。</p>
<h2 id="3-VHDL电路描述"><a href="#3-VHDL电路描述" class="headerlink" title="3. VHDL电路描述"></a>3. VHDL电路描述</h2><p>根据以上电路原理，设计如下VHDL电路描述，其中分为实体<code>dataStack</code>，依附于实体的结构体<code>StackBody</code>，其中包含三个进程分别为入栈进程<code>WrProc</code>，出栈进程<code>RdProc</code>和动态调整进程<code>PntCon</code>；描述语句为IEEE标准，引用IEEE逻辑器件程序库，使用程序包<code>IEEE.STD_LOGIC_1164</code>与<code>IEEE.STD_LOGIC_UNSIGNED</code>，描述代码如下：</p>
<figure class="highlight vhdl"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">LIBRARY</span> IEEE;</span><br><span class="line"><span class="keyword">USE</span> IEEE.STD_LOGIC_1164.<span class="keyword">ALL</span>;</span><br><span class="line"><span class="keyword">USE</span> IEEE.STD_LOGIC_UNSIGNED.<span class="keyword">ALL</span>;</span><br><span class="line"><span class="keyword">ENTITY</span> dataStack <span class="keyword">IS</span></span><br><span class="line">  <span class="keyword">PORT</span>(D:<span class="keyword">INOUT</span> <span class="built_in">STD_LOGIC_VECTOR</span>(<span class="number">7</span> <span class="keyword">DOWNTO</span> <span class="number">0</span>);</span><br><span class="line">       CS,RD,WR:<span class="keyword">IN</span> <span class="built_in">STD_LOGIC</span>;</span><br><span class="line">		 Empt,Full:<span class="keyword">OUT</span> <span class="built_in">STD_LOGIC</span>);</span><br><span class="line"><span class="keyword">END</span> dataStack;</span><br><span class="line"><span class="keyword">ARCHITECTURE</span> StackBody <span class="keyword">OF</span> dataStack <span class="keyword">IS</span></span><br><span class="line">  <span class="keyword">TYPE</span> mMem <span class="keyword">IS</span> <span class="keyword">ARRAY</span>(<span class="number">0</span> <span class="keyword">TO</span> <span class="number">7</span>)<span class="keyword">OF</span> <span class="built_in">STD_LOGIC_VECTOR</span>(<span class="number">7</span> <span class="keyword">DOWNTO</span> <span class="number">0</span>);</span><br><span class="line">  <span class="keyword">SIGNAL</span> DSeg:mMem;</span><br><span class="line">  <span class="keyword">SIGNAL</span> EmptF:<span class="built_in">STD_LOGIC</span>:=<span class="string">&#x27;1&#x27;</span>;</span><br><span class="line">  <span class="keyword">SIGNAL</span> FullF:<span class="built_in">STD_LOGIC</span>:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">  <span class="keyword">SIGNAL</span> pWr:<span class="built_in">INTEGER</span> <span class="keyword">RANGE</span> <span class="number">0</span> <span class="keyword">TO</span> <span class="number">8</span> :=<span class="number">0</span>;</span><br><span class="line">  <span class="keyword">SIGNAL</span> pRd:<span class="built_in">INTEGER</span> <span class="keyword">RANGE</span> <span class="number">0</span> <span class="keyword">TO</span> <span class="number">8</span> :=<span class="number">0</span>;</span><br><span class="line"><span class="keyword">BEGIN</span></span><br><span class="line">  WrProc:<span class="keyword">PROCESS</span>(RD,CS,EmptF,WR,D,pRd)</span><br><span class="line">    <span class="keyword">VARIABLE</span> iWr:<span class="built_in">INTEGER</span> <span class="keyword">RANGE</span> <span class="number">0</span> <span class="keyword">TO</span> <span class="number">8</span> :=<span class="number">0</span>;</span><br><span class="line">	 <span class="keyword">VARIABLE</span> iFull:<span class="built_in">STD_LOGIC</span>:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">	 <span class="keyword">VARIABLE</span> iDeta:<span class="built_in">STD_LOGIC</span>:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">  <span class="keyword">BEGIN</span></span><br><span class="line">    <span class="keyword">IF</span> RD=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> CS=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> EmptF=<span class="string">&#x27;0&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">	   iDeta:=<span class="string">&#x27;1&#x27;</span>;</span><br><span class="line">		iFull:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">	 <span class="keyword">ELSIF</span> RISING_EDGE(WR) <span class="keyword">AND</span> CS=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> iFull=<span class="string">&#x27;0&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">	   <span class="keyword">IF</span> iDeta=<span class="string">&#x27;1&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">		  iWr:=pRd;</span><br><span class="line">		<span class="keyword">END</span> <span class="keyword">IF</span>;</span><br><span class="line">		DSeg(iWr)&lt;=D;</span><br><span class="line">		<span class="keyword">IF</span> iWr=<span class="number">7</span> <span class="keyword">THEN</span></span><br><span class="line">		  iFull:=<span class="string">&#x27;1&#x27;</span>;</span><br><span class="line">		<span class="keyword">END</span> <span class="keyword">IF</span>;</span><br><span class="line">		iWr:=iWr+<span class="number">1</span>;</span><br><span class="line">		iDeta:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">	 <span class="keyword">END</span> <span class="keyword">IF</span>;</span><br><span class="line">     pWr&lt;=iWr;</span><br><span class="line">	 FullF&lt;=iFull;</span><br><span class="line">  <span class="keyword">END</span> <span class="keyword">PROCESS</span> WrProc;</span><br><span class="line">  RdProc:<span class="keyword">PROCESS</span>(CS,RD,EmptF,DSeg,pRd)</span><br><span class="line">  <span class="keyword">BEGIN</span></span><br><span class="line">	 <span class="keyword">IF</span> RD=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> CS=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> EmptF=<span class="string">&#x27;0&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">	   D&lt;=DSeg(pRd);</span><br><span class="line">	 <span class="keyword">ELSE</span></span><br><span class="line">		D&lt;=<span class="string">&quot;ZZZZZZZZ&quot;</span>;</span><br><span class="line">	 <span class="keyword">END</span> <span class="keyword">IF</span>;</span><br><span class="line">  <span class="keyword">END</span> <span class="keyword">PROCESS</span> RdProc;</span><br><span class="line">  PntCon:<span class="keyword">PROCESS</span>(WR,CS,FullF,pWr,RD)</span><br><span class="line">    <span class="keyword">VARIABLE</span> iRd:<span class="built_in">INTEGER</span> <span class="keyword">RANGE</span> <span class="number">0</span> <span class="keyword">TO</span> <span class="number">8</span> :=<span class="number">0</span>;</span><br><span class="line">	 <span class="keyword">VARIABLE</span> iEmpt:<span class="built_in">STD_LOGIC</span>:=<span class="string">&#x27;1&#x27;</span>;</span><br><span class="line">	 <span class="keyword">VARIABLE</span> iDeta:<span class="built_in">STD_LOGIC</span>:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">  <span class="keyword">BEGIN</span></span><br><span class="line">    <span class="keyword">IF</span> WR=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> CS=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> FullF=<span class="string">&#x27;0&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">	   iDeta:=<span class="string">&#x27;1&#x27;</span>;</span><br><span class="line">		iEmpt:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">	 <span class="keyword">ELSIF</span> FALLING_EDGE(RD) <span class="keyword">AND</span> CS=<span class="string">&#x27;0&#x27;</span> <span class="keyword">AND</span> iEmpt=<span class="string">&#x27;0&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">	   <span class="keyword">IF</span> iDeta=<span class="string">&#x27;1&#x27;</span> <span class="keyword">THEN</span></span><br><span class="line">		  iRd:=pWr-<span class="number">1</span>;</span><br><span class="line">		<span class="keyword">ELSIF</span> iRd&gt;<span class="number">0</span> <span class="keyword">THEN</span></span><br><span class="line">		  iRd:=iRd-<span class="number">1</span>;</span><br><span class="line">		<span class="keyword">ELSE</span></span><br><span class="line">		  iEmpt:=<span class="string">&#x27;1&#x27;</span>;</span><br><span class="line">		<span class="keyword">END</span> <span class="keyword">IF</span>;</span><br><span class="line">		iDeta:=<span class="string">&#x27;0&#x27;</span>;</span><br><span class="line">	 <span class="keyword">END</span> <span class="keyword">IF</span>;</span><br><span class="line">	 pRd&lt;=iRd;</span><br><span class="line">	 EmptF&lt;=iEmpt;</span><br><span class="line">  <span class="keyword">END</span> <span class="keyword">PROCESS</span> PntCon;</span><br><span class="line">  Empt&lt;=EmptF;</span><br><span class="line">  Full&lt;=FullF;</span><br><span class="line"><span class="keyword">END</span> StackBody; </span><br></pre></td></tr></table></figure>
<p>堆栈电路<code>dataStack</code>在正常工作时，数据的出入栈动作均会影响读写指针pRd与pWr；写进程<code>WrProc</code>响应信号WR的上升沿，CS为低电平有效且堆栈<code>dataStack</code>不为满状态，若上次操作为出栈<strong>（iDeta =‘1’）</strong>，<code>WrProc</code>获取读指针pRd，根据pRd计算当前写指针pWr。当上次操作为入栈<strong>（iDeta=‘0’）</strong>时，如果pWr到达栈顶，将堆栈满标志<code>iFull</code>置位，调整写指针pWr。然后写进程<code>WrProc</code>获取数据总线D，送入堆栈存储区<code>DSeg</code>中由pWr指定的存储单元<code>DSeg(pWr)</code>，同时清除标志<code>iDeta</code>。<br>由于写指针pWr的计算与上次栈操作类型有关，进程<code>WrProc</code>监测读信号RD，若RD发生变化、CS有效且堆栈不为空（EmptF为“0”），进程<code>WrProc</code>将<code>iDeta</code>置位，供<code>WrProc</code>执行入栈操作时计算pWr使用。<br>进程<code>PntCon</code>计算堆栈电路的读指针pRd，进程响应读信号的下降沿，若CS有效且堆栈不为空（EmptF为“0”），则计算堆栈读指针pRd，执行出栈操作。进程<code>RdProc</code>响应读信号RD，在CS有效且堆栈不为空时，将读指针pRd对应的堆栈存储单元<code>DSeg(pRd)</code>送上数据总线D。</p>
<h2 id="4-电路的实现"><a href="#4-电路的实现" class="headerlink" title="4. 电路的实现"></a>4. 电路的实现</h2><p>使用<strong>QuartusⅡ 13.0</strong>版本进行电路搭建以及仿真。首先进行新建项目，将VHDL描述程序加入设计项目并作为顶层实体，实现预定的堆栈功能电路。顶层实体以及项目名称需要保持一致，均命名为<code>dataStack</code>。同时实体的VHDL描述程序文件名称需要与顶层实体名称一一对应，命名为<code>dataStack</code>。本次电路载体选择<strong>Cyclone Ⅲ</strong>系列的<strong>EP3C40Q240C8N</strong>来实现预定电路，进行编译之后如图4.1所示。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/4.1.png" alt="图4.1 Quartus Ⅱ编译状态图"></p>
<p>其中根据编译总结报告可知（图4.2），采用<strong>EP3C40Q240C8N</strong>器件实现目标堆栈电路dataStack需要占用<strong>宏单元（Total logic elements）</strong>101个，所占用总数小于器件所提供宏单元的1%；实现目标逻辑占用器件端口（Pins）13个，占器件所提供的I/O端口总数的10%。器件<strong>EP3C40Q240C8N</strong>采用129脚的TQFP封装，速度等级为<strong>Level-9</strong>，封装形式及器件大小，速度等级对于实现堆栈电路来说大材小用，但是应学校器材限制，使用<strong>EP3C40Q240C8N</strong>器件来实现dataStack电路十分合理。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/4.2.png" alt="图4.2 编译总结报告图"></p>
<p>因此最终指定器件为<strong>EP3C40Q240C8N</strong>，考虑到后续制板、布局、布线的合理性以及调试的方便性，堆栈电路dataStack的引脚分配与器件指定情况如图4.3所示。图中带阴影引脚为已分配信号的引脚，从引脚18到引脚142,按照逆时针顺序，端口上分配的信号依次为：片选信号CS、双向数据总线的数据端口D、堆栈电路dataStack空标志Empt、堆栈电路dataStack满标志Full、计算机并行接口的读信号RD、计算机并行接口的写信号WR。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/4.3.png" alt="图4.3 引脚分配与器件指定情况"></p>
<p>表4.4给出了堆栈电路dataStack实现器件EP3C40Q240C8N引脚与I/O信号的详细对应关系。</p>
<hr>
<center>表4.4 堆栈电路dataStack的引脚信号详细分配状况</center>

<table>
<thead>
<tr>
<th>To</th>
<th>Direction</th>
<th>Location</th>
<th align="center">I/O Bank</th>
<th>VREF Group</th>
<th>Fitter Location</th>
</tr>
</thead>
<tbody><tr>
<td>CS</td>
<td>Input</td>
<td>PIN_18</td>
<td align="center">1</td>
<td>B1_N2</td>
<td>PIN_18</td>
</tr>
<tr>
<td>D(7)</td>
<td>Bidir</td>
<td>PIN_21</td>
<td align="center">1</td>
<td>B1_N3</td>
<td>PIN_21</td>
</tr>
<tr>
<td>D(6)</td>
<td>Bidir</td>
<td>PIN_38</td>
<td align="center">2</td>
<td>B2_N0</td>
<td>PIN_38</td>
</tr>
<tr>
<td>D(5)</td>
<td>Bidir</td>
<td>PIN_80</td>
<td align="center">3</td>
<td>B3_N1</td>
<td>PIN_80</td>
</tr>
<tr>
<td>D(4)</td>
<td>Bidir</td>
<td>PIN_78</td>
<td align="center">3</td>
<td>B3_N1</td>
<td>PIN_78</td>
</tr>
<tr>
<td>D(3)</td>
<td>Bidir</td>
<td>PIN_76</td>
<td align="center">3</td>
<td>B3_N1</td>
<td>PIN_76</td>
</tr>
<tr>
<td>D(2)</td>
<td>Bidir</td>
<td>PIN_73</td>
<td align="center">3</td>
<td>B3_N2</td>
<td>PIN_73</td>
</tr>
<tr>
<td>D(1)</td>
<td>Bidir</td>
<td>PIN_70</td>
<td align="center">3</td>
<td>B3_N2</td>
<td>PIN_70</td>
</tr>
<tr>
<td>D(0)</td>
<td>Bidir</td>
<td>PIN_69</td>
<td align="center">3</td>
<td>B3_N2</td>
<td>PIN_69</td>
</tr>
<tr>
<td>Empt</td>
<td>Output</td>
<td>PIN_139</td>
<td align="center">5</td>
<td>B3_N2</td>
<td>PIN_139</td>
</tr>
<tr>
<td>Full</td>
<td>Output</td>
<td>PIN_142</td>
<td align="center">5</td>
<td>B5_N1</td>
<td>PIN_142</td>
</tr>
<tr>
<td>RD</td>
<td>Input</td>
<td>PIN_37</td>
<td align="center">2</td>
<td>B2_N0</td>
<td>PIN_37</td>
</tr>
<tr>
<td>WR</td>
<td>Input</td>
<td>PIN_39</td>
<td align="center">2</td>
<td>B2_N0</td>
<td>PIN_39</td>
</tr>
</tbody></table>
<hr>
<h2 id="5-电路分析与仿真测试"><a href="#5-电路分析与仿真测试" class="headerlink" title="5. 电路分析与仿真测试"></a>5. 电路分析与仿真测试</h2><p>在<strong>QuartusⅡ</strong>中新建一个名为dataStack的vwf逻辑功能仿真波形文件，将图中的仿真栅格（Grid Size）大小设置为20ns，仿真总时长（Set End Time）设置为3us。导入信号并设置波形输入信号（如图5.1）。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/5.1.png" alt="图5.1"></p>
<p>其中信号\PntCon:iRd为堆栈电路dataStack的读指针，与其相对应，信号\WrProc:iWr为堆栈电路dataStack的写指针；信号D为计算机并行接口8位双向数据端口的设定值，信号DATA为堆栈电路dataStack工作时8位双向数据端口D的信号变化情况。<br>在上述仿真激励中的时间段30-450ns内，并行接口写信号WR连续产生下降沿，向堆栈电路dataStack持续写入10个数据。此时，堆栈电路dataStack的工作时序仿真如图5.2所示。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/5.2.png" alt="图5.2"></p>
<p>从时刻30ns开始并行接口向堆栈电路dataStack持续送入数据01-10，写指针iWr依次增加，当写至数据8时，满标志Full变为高电平，堆栈满。在时间段520-580ns内，RD连续发出读脉冲，DATA送出最后的压栈数据8、7。在时间段660-720ns内，将数据10、11压栈，Full重新变为高电平。图5.3所示为dataStack持续出栈情况。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/5.3.png" alt="图5.3"></p>
<p>从840ns时刻开始，RD连续发出读脉冲，数据总线DATA端连续送出数据12、11、6、5、4、3、2、1，与前文的压栈数据顺序一一对应。在840ns时刻，RD变为低电平，堆栈dataStack开始送出数据，满标志Full迅速变为低电平；送出8个数据后，空标志Empt置位，堆栈清空。<br>当堆栈满后，数据随机出栈时的堆栈电路工作时序仿真结果如图5.4所示。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/5.4.png" alt="图5.4"></p>
<p>从时刻1.30us开始，CS有效，WR连续发出写脉冲，DATA端数据13-20依次被压入堆栈dataStack。压栈开始，空标志Empt迅速变为低电平。当8当个数据完成压栈后，堆栈满标志Full置位。在时刻1.76us处，RD连续发出4个随机的读信号，栈顶的4个数据20、19、18、17被送上dataStack电路的数据总线DATA，此时，堆栈内顺序保留数据16、15、14、13。</p>
<p><img src= "" data-lazy-src="/2020/07/27/edadesign/5.5.png" alt="图5.5"></p>
<p>图5.5所示为随机压栈至满栈后，持续出栈时电路的工作时序仿真结果。从时刻1.32us开始，端口WR上连续出现写脉冲，数据23-26被压入堆栈，堆栈满标志Full被置为高电平，堆栈dataStack进入满状态。从时刻2.30us开始，端口RD持续发出读脉冲，堆栈内的数据被依次送至DATA端口，数据序列为26、25、24、23、16、15、14与13，数据顺序符合压栈顺序。<br>以上，结合电路的预定功能，通过4种状况对堆栈电路dataStack进行了初步的测试以及逻辑仿真校验，电路动作与原定功能和工作时序一致。堆栈电路dataStack的其他工作时序分析与以上分析基本类似，电路达到设计要求。</p>
<h2 id="6-设计总结"><a href="#6-设计总结" class="headerlink" title="6. 设计总结"></a>6. 设计总结</h2><p>电子设计自动化（EDA）是二十一世纪最重要的应用科学之一，在计算机、数控机床、机器人、互联网、数字媒体、人工智能等方面举足轻重。</p>
</article><div class="post-copyright"><div class="post-copyright__author"><span class="post-copyright-meta">文章作者: </span><span class="post-copyright-info"><a href="mailto:undefined">哲铭</a></span></div><div class="post-copyright__type"><span class="post-copyright-meta">文章链接: </span><span class="post-copyright-info"><a href="https://jimmyliang-lzm.github.io/2020/07/27/edadesign/">https://jimmyliang-lzm.github.io/2020/07/27/edadesign/</a></span></div><div class="post-copyright__notice"><span class="post-copyright-meta">版权声明: </span><span class="post-copyright-info">本博客所有文章除特别声明外，均采用 <a href="https://creativecommons.org/licenses/by-nc-sa/4.0/" target="_blank">CC BY-NC-SA 4.0</a> 许可协议。转载请注明来自 <a href="https://jimmyliang-lzm.github.io" target="_blank">Jimmy's TechBlog</a>！</span></div></div><div class="tag_share"><div class="post-meta__tag-list"><a class="post-meta__tags" href="/tags/EDA%E8%AE%BE%E8%AE%A1/">EDA设计</a><a class="post-meta__tags" href="/tags/FPGA/">FPGA</a><a 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href="#3-VHDL%E7%94%B5%E8%B7%AF%E6%8F%8F%E8%BF%B0"><span class="toc-text">3. VHDL电路描述</span></a></li><li class="toc-item toc-level-2"><a class="toc-link" href="#4-%E7%94%B5%E8%B7%AF%E7%9A%84%E5%AE%9E%E7%8E%B0"><span class="toc-text">4. 电路的实现</span></a></li><li class="toc-item toc-level-2"><a class="toc-link" href="#5-%E7%94%B5%E8%B7%AF%E5%88%86%E6%9E%90%E4%B8%8E%E4%BB%BF%E7%9C%9F%E6%B5%8B%E8%AF%95"><span class="toc-text">5. 电路分析与仿真测试</span></a></li><li class="toc-item toc-level-2"><a class="toc-link" href="#6-%E8%AE%BE%E8%AE%A1%E6%80%BB%E7%BB%93"><span class="toc-text">6. 设计总结</span></a></li></ol></div></div><div class="card-widget card-recent-post"><div class="item-headline"><i class="fas fa-history"></i><span>最新文章</span></div><div class="aside-list"><div class="aside-list-item"><a class="thumbnail" href="/2021/10/05/Get_bilibili_cookie/" title="【教程】如何获取B站用户Cookie"><img src= "" data-lazy-src="/source_storage/2233.jpg" onerror="this.onerror=null;this.src='/img/404.jpg'" alt="【教程】如何获取B站用户Cookie"/></a><div class="content"><a class="title" href="/2021/10/05/Get_bilibili_cookie/" title="【教程】如何获取B站用户Cookie">【教程】如何获取B站用户Cookie</a><time datetime="2021-10-06T03:00:00.000Z" title="发表于 2021-10-06 11:00:00">2021-10-06</time></div></div><div class="aside-list-item"><a class="thumbnail" href="/2021/08/31/mecanum-kinematics/" title="【学术】4-麦克纳姆轮平台运动学建模"><img src= "" data-lazy-src="/source_storage/mecan_ka.gif" onerror="this.onerror=null;this.src='/img/404.jpg'" alt="【学术】4-麦克纳姆轮平台运动学建模"/></a><div class="content"><a class="title" href="/2021/08/31/mecanum-kinematics/" title="【学术】4-麦克纳姆轮平台运动学建模">【学术】4-麦克纳姆轮平台运动学建模</a><time datetime="2021-09-01T03:00:00.000Z" title="发表于 2021-09-01 11:00:00">2021-09-01</time></div></div><div class="aside-list-item"><a class="thumbnail" href="/2021/02/09/Java-Note-01/" title="【Java学习】Java入门笔记1"><img src= "" data-lazy-src="/source_storage/java.jpg" onerror="this.onerror=null;this.src='/img/404.jpg'" alt="【Java学习】Java入门笔记1"/></a><div class="content"><a class="title" href="/2021/02/09/Java-Note-01/" title="【Java学习】Java入门笔记1">【Java学习】Java入门笔记1</a><time datetime="2021-02-10T04:06:00.000Z" title="发表于 2021-02-10 12:06:00">2021-02-10</time></div></div><div class="aside-list-item"><a class="thumbnail" href="/2021/01/31/PID-DCMotor-Simulate/" title="【学习手记】基于AT89C52单片机的PID直流电机控制系统仿真"><img src= "" data-lazy-src="/source_storage/Proteus.jpg" onerror="this.onerror=null;this.src='/img/404.jpg'" alt="【学习手记】基于AT89C52单片机的PID直流电机控制系统仿真"/></a><div class="content"><a class="title" href="/2021/01/31/PID-DCMotor-Simulate/" title="【学习手记】基于AT89C52单片机的PID直流电机控制系统仿真">【学习手记】基于AT89C52单片机的PID直流电机控制系统仿真</a><time datetime="2021-01-31T12:50:00.000Z" title="发表于 2021-01-31 20:50:00">2021-01-31</time></div></div><div class="aside-list-item"><a class="thumbnail" href="/2021/01/29/Matlab_Robot_simulation/" title="【学习手记】MATLAB与机器人仿真项目训练"><img src= "" data-lazy-src="/source_storage/matlabrobotsimulate.png" onerror="this.onerror=null;this.src='/img/404.jpg'" alt="【学习手记】MATLAB与机器人仿真项目训练"/></a><div class="content"><a class="title" href="/2021/01/29/Matlab_Robot_simulation/" title="【学习手记】MATLAB与机器人仿真项目训练">【学习手记】MATLAB与机器人仿真项目训练</a><time datetime="2021-01-30T05:14:00.000Z" title="发表于 2021-01-30 13:14:00">2021-01-30</time></div></div></div></div></div></div></main><footer id="footer"><div id="footer-wrap"><div class="copyright">&copy;2020 - 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